1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
A semiconductor device is known that incorporates a plurality of capacitive elements. Such a semiconductor device is configured, for example, with bipolar integrated circuits. See, for example, Japanese Patent Application Laid-open Publication No. 1999-312784. FIG. 6 shows an example of a cross-sectional structure of a unit capacitive element used in the bipolar integrated circuit. As shown in FIG. 6, a unit capacitive element Cy comprises a P-type semiconductor substrate 1, a P-type isolation region 2, an island region 3 made up of an N-type layer surrounded by the isolation region 2, an N-type bottom electrode region 4 formed on the surface of the island region, an oxide film 5, a dielectric thin film 6 such as silicon nitride film, an aluminum top electrode 7 and a lead-out electrode 8 of a bottom electrode. Its capacitance value is roughly determined by the area of the dielectric thin film 6 in contact with the surface of the bottom electrode 4. This area is equal to the area of an opening portion 5a cleared of the oxide film 5 covering the bottom electrode 4.
As shown in a plan view of FIG. 7, capacitive element groups Ca and Cb are configured through parallel connection of the unit capacitive elements Cy. In the case of a capacitance ratio of 5:15 (1:3), five of the unit capacitive elements Cy are arranged side by side to form the capacitive element Ca. On the other hand, 15 of the unit capacitive elements Cy are arranged side by side to form the capacitive element Cb. The unit capacitive elements Cy of each of the capacitive element groups Ca and Cb are connected to a respective common electrode 12, 13 with connection electrodes 11.
The unit capacitive elements Cy making up each of the capacitive element groups Ca and Cb are connected in parallel each by the electrode wire 11 connected to the top electrode 7. In the case of a three-layer aluminum wiring, the electrode wire is formed by the third wire layer, i.e., the wire layer located at the topmost. The bottom electrode 4 of each of the unit capacitive elements Cy is connected to ground potential GND.
Configuring the above capacitive element groups Ca and Cb presents problems in design and layout pattern of the unit capacitive elements Cy. That is, it is necessary, out of demands for downsizing and higher accuracy of semiconductor devices, to use the smallest possible unit capacitive elements for capacitive element groups for highly accurate capacitance value and capacitance ratio.
In general, however, the smaller the capacitance value of the unit capacitive element Cy for smaller area, the poorer the accuracy of the overall capacitance value and capacitance ratio. For this reason, it is necessary to reduce the area without degrading their accuracy.
However, the conventional design of the unit capacitive element Cy and the aforementioned layout method shown in FIG. 7 have been unfit for high accuracy in capacitance value and ratio and downsizing. That is, if the unit capacitive element Cy is simply reduced in size for downsizing, the capacitance value of the entire capacitive element group falls outside a desired range of values, resulting in larger error. One of the factors contributing to this error is effects of parasitic capacitance of the bottom electrode of each of the unit capacitive elements Cy. The parasitic capacitance includes, for example, parasitic capacitance to ground (electrode-to-ground parasitic capacitance). Among the effects of parasitic capacitance are, for instance, defects including error in circuit characteristics caused by parasitic capacitance, such as error in divided voltage value when the capacitive element group is used in a voltage dividing or other circuit as a constituent element.